专用集成电路与系统国家重点实验室
讲座信息


时 间:2016年3月24日(周四)上午10:00-11:30
地 点:张江校区微电子楼369室

(1)
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems
Yeong-Luh Ueng(National Tsing Hua University, Hsinchu, Taiwan)

Abstract
This talk presents a high-throughput, area-efficient and energy-efficient iterative detection and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems. A layered non-resetting IDD technique is used to minimize the number of inner iterations for a required error performance. An area-efficient minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is devised to simplify matrix inversion. A detector-decoder interface that is used to exchange soft messages efficiently is proposed. Given the throughput specifications, inner and outer loops are optimally combined to maximize the error performance. The design specifications defined in the IEEE 802.11n standard are adopted as the design target. A 4x4 antenna configuration with BPSK, QPSK, 16-QAM modulations are realized in silicon. Fabricated in 40 nm technology, the chip integrates 998k logic gates in 1.33 and achieves a maximum throughput of 794 Mb/s. The chip dissipates 135 mW at 0.9 V, achieving an energy efficiency of 170 pJ/bit.

Biography
Yeong-Luh Ueng received the Ph.D. degree in communication engineering from the National Taiwan University, Taipei, Taiwan, in 2001. From 2001 to 2005, he was with a private communication technology company, where he focused on the design and development of various wireless chips. Since December 2005, he has been a member of the faculty of the National Tsing Hua University, Hsinchu, Taiwan, where he is currently an Associate Professor with the Department of Electrical Engineering and the Institute of Communications Engineering. His research interests include coding theory, wireless communications, and communication ICs. He has published 27 IEEE journal papers including 23 full papers. He also has presented 18 technical contributions related to the IEEE 802.16 standard. He was also invited to speak at the 6th International Symposium on Turbo Codes & Iterative Information Processing, one of the most well-known symposiums in the area of error correction coding. He was elected as an honorary member of the Phi Tau Phi Scholastic Honor Society. He also earned the Excellent Industry-Academia Collaboration Award, National Tsing-Hua University, in 2013 and 2014. He has been the recipient of the Distinguished Young Scholar Award from Taiwan IC Design society in 2015.

 

(2)
Classical and New Perspectives of Physical Implementations of Algorithms
Chuan Zhang (Southeast University, Nanjing, China)

Abstract
In this talk the speaker is going to give his understanding of physical implementations of algorithms. Both classical and new perspectives are included. The 5G baseband processing algorithms will be employed as running examples to show how we carry out efficient physical implementations. New and alternative perspective including stochastic computing and DNA computing will also be mentioned in brief.

Biography
Dr. Chuan Zhang is now an associate professor of National Mobile Communications Re-search Laboratory, School of Information Science and Engineering, Southeast University, Nanjing, China. He received B.E. degree in microelectronics and M.E. degree in VLSI design from Nanjing University, Nanjing, China, in 2006 and 2009, respectively. He received both M.S.E.E. degree and Ph.D. degree in Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities (UMN), USA, in 2012. His current research interests include 5G communication system designs, low-power high-speed VLSI design, specifically VLSI design for digital signal processing, digital communications (with emphasis on error-control coding and cryptography), quantum information theory, and bio-chemical synthesis implementation. As the first author, Dr. Zhang has published papers in journals such as IEEE Transactions on Circuits and Systems I and II, IEEE Trans-actions on Signal Processing, and refereed proceedings such as ISCAS, ICC, Asilomar, APCCAS, SOCC, and so on. He is a reviewer for more than thirty key journals and conferences in the fields of communication, circuits and systems, and signal processing. He served as a Technical Program Committee member for ASQED'15 and SiPS'15 and session chair for APCCAS'14, WCSP'14, ISCAS'15, SOCC'15, DSP'15, and ASICON'15. He has also successfully organized special sessions for ISCAS'15, SOCC'15, DSP'15, SiPS'15, ASICON'15, ICASSP'16. Dr. Zhang is a member of IEEE and a member of Seasonal School Committee of the IEEE Signal Processing Society, Circuits & Systems for Communications (CASCOM) TC, VLSI Systems & Applications (VSA) TC, and Digital Signal Processing (DSP) TC of IEEE CAS Society. He was also a (co-)recipient of the Best Student Paper Award of IEEE International Conference on ASIC (ASICON) in 2015, the Best Paper Award Nomination of IEEE Workshop on Signal Processing Systems (SiPS) in 2015, the Merit Student Paper Award of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2008, Three-Year University-Wide Graduate School Fellow-ship of UMN, Doctoral Dissertation Fellowship of UMN, the Carnegie Mellon University Graduate Fellowship (declined), and the Four-Year CSC Graduate Fellowship of Stanford University (declined).

 
 
 
 

 

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