讲座信息
The coming age of digital implementation flow for modern chip designs

题  目:The coming age of digital implementation flow for modern chip designs
报告人:Zhuo Li (Cadence)
时  间:2015年7月2日(周四)上午10:00-11:00
地  点:张江校区微电子楼369室

Abstract
As the manufacturing cost continues to increase in the advanced technology nodes beyond 20 nm, there exits more demanding requirement for area and power efficient devices. Therefore, designers have to pack more and more logic functionalities into a small-sized die to balance the fabrication cost and chip power. Naturally, it becomes increasingly challenging to achieve design closure on these enormous chips with tight performance and power constraints. Traditional digital implementation flow needs to revitalize itself to handle more constraints than ever, such as congestion and timing inside placement, optimization with multiple layers of metal, hierarchical design styles and more embedded IPs, complicated logic structures, complicated design and manufacturing rules, aggressive power budgets, .etc. The next generation synthesis and implementation flow need to attack all of these problems, while still achieving faster turn-around-time at the same time to meet the short time-to-market. The field needs new innovations!

This talk will discuss latest problems and challenges in physical implementation flow related to placement, buffering, layer assignment, congestion mitigation, logic synthesis, clocking, routing, as well as some previous published research results and latest solutions from Industry. If time permits, The speaker will also discuss CAD Contest, DAC 2016, overview of Cadence Design Systems and career opportunities.

Biography
Zhuo Li received the B.S. and M.S. degree in electrical engineering from Xi'an Jiaotong University, in 1998 and 2001, respectively, and the Ph.D. degree in computer engineering from Texas A&M University, College Station, in 2005. He was enrolled in the special class for the gifted youth program at age 13. After graduation, he co-founded Pextra Corp, which was a startup specializing in parasitic extraction and acquired by Mentor Graphics Corp. in 2009.  From 2006 to 2014, he was a Research Staff Member at IBM T.J. Watson Research Center and Austin Research Lab developing IBM flagship physical design flow and tools. The tools are used to construct P7/P7+/P8/Z series microprocessors, gaming chips and high performance ASICs across technology nodes from 90 to 14 nm. He has received five IBM Outstanding Technical Achievement Awards, one IBM Outstanding Contributor Award, and 4 IBM Research O-level accomplishment awards. He was a member of IBM SyNapse (neuron chip) project. Currently Dr. Li is a Software Architect at Cadence Design Systems developing next generation digital implementation flow product Innovus and synthesis product Genus.

      Dr. Li has filed 63 patents with 47 issued. He has published over 70 conference and journal papers, and has received the Best Paper Award at ASPDAC 2007, the IEEE Circuits and System Society Outstanding Young Author Award at DAC 2007, three Best Paper Award Nominations at ISPD, ICCAD and ISQED, and two Best Paper Award Nominations from IEEE TCAD. He has received many IEEE/ACM service awards including ACM Technical Leadership Award from ACM SIGDA, SRC Mahboob Khan Outstanding Industry Liaison/Associate Award, DAC Service Award, IEEE Region 5 Outstanding Individual Member Achievement Award (twice).
      In 2013, as the first winner from the industry, he received IEEE CEDA Early Career Award, the top award for young researchers in EDA area. In 2015, the National Academy of Engineering has selected Zhuo Li to participate in the US Frontiers of Engineering Symposium, which is intended to select from among the nation’s top engineering talent in both academia and industry for ages 30-45. He has been serving as TPC sub-committee Chair or committee members for all major conferences in EDA area, such as DAC, ICCAD and DATE. He was the Guest Editor of VLSI Design Journal Special Issue “CAD for Gigascale SoC Design and Verification Solutions”. He was the Contest Chair of TAU Power Grid Simulation Contest, Chair of 2013 CAD Contest and General Co-Chair of 2014 and 2015 DAC Ph.D. Forum. He is an Associate Editor of IEEE Transactions of Computer-Aided Design, and on Executive Committee of Design Automation Conference (DAC) as Designer Track Co-Chair in 2016.

     Dr. Li currently serves as the secretary of IEEE Central Texas Section and he was the founding Chair of IEEE CEDA Chapter of Central Texas Section. When he was the Chapter Chair of IEEE CAS/SSC Chapter of Central Texas Section, the chapter won the IEEE Circuits and Systems Society 2014 Chapter of the Year Award, 2011 Region 1 to 7 Chapter of the Year Award and IEEE Solid State Circuits Society 2011 Outstanding Chapter Award.  Dr. Li is an IEEE Senior Member.

 
 
 
 

 

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