专用集成电路与系统国家重点实验室
讲座信息


题  目:High Design Productivity for High-Performance and Energy-Efficient Circuits
报告人:Deming Chen (University of Illinois, Urbana-Champaign)
时  间:2015年5月28日(周四)下午16:00-17:00
地  点:张江校区微电子楼389室


Abstract
A significant problem facing the semiconductor industry is that the design productivity for complex ICs has been lagging behind. High-level synthesis (HLS) has been touted as a solution to this problem, as it can significantly reduce the number of man hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HLS can be noticeably worse than that of manual RTL design. In this talk, Dr. Chen will present a set of new techniques to drastically improve HLS solutions, which not only improve circuit performance and energy efficiency but also circuit reliability and robustness. As one example, our code transformation and optimization using polyhedral model can enable data streaming across two communicating hardware modules through HLS, which achieved 30X execution speedup over the baseline on average.

Biography
Dr. Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He worked as a software engineer between 1995-1999 and 2001-2002. He is a professor in the ECE department of University of Illinois, Urbana-Champaign. His current research interests include system-level and high-level synthesis, nano-systems design and nano-centric CAD techniques, GPU and reconfigurable computing, hardware security, and computational genomics.
Dr. Chen is a technical committee member for a series of conferences and symposia, including FPGA, ASPDAC, ICCD, ISQED, DAC, ICCAD, DATE, ISLPED, FPL, HiPC, etc. He also served as session chair, panelist, panel organizer, or moderator for some of these and other conferences. He is the TPC Subcommittee or Track Chair for ASPDAC'09-11 and '13, ISVLSI'09, ISCAS'10-11, VLSI-SoC'11, ICCAD'12, ICECS'12, ISLPED'14, and ICCD'14-15, etc. He is the General Chair for SLIP'12, the CANDE Workshop Chair in 2011, the Program Chair for PROFIT'12, the Program Chair for FPGA'15, and the Program Co-chair for GLSVLSI'17. He is or has been an associated editor for TCAD (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems), TODAES (ACM Transactions on Design Automation of Electronic Systems), TVLSI (IEEE Transactions on Very Large Scale Integration Systems), TCAS-I (IEEE Transactions on Circuits and Systems I), JCSC (Journal of Circuits, Systems and Computers), and JOLPE (Journal of Low Power Electronics). He obtained the Achievement Award for Excellent Teamwork from Aplus Design Technologies in 2001, the Arnold O. Beckman Research Award from UIUC in 2007, the NSF CAREER Award in 2008, and five Best Paper Awards for ASPDAC'09, SASP'09, FCCM'11, SAAHPC'11, and CODES+ISSS'13. He is included in the List of Teachers Ranked as Excellent in 2008. He received the ACM SIGDA Outstanding New Faculty Award in 2010, and IBM Faculty Award in 2014 and 2015. He is a senior member of IEEE, a distinguished visiting professor of Fudan University, and the Donald Biggar Willett Faculty Scholar.
Dr. Chen was involved in two startup companies. He implemented his published algorithm on CPLD technology mapping when he was a software engineer in Aplus Design Technologies, Inc. in 2001, and the software was exclusively licensed by Altera and distributed to many customers of Altera worldwide. He is one of the inventors of the xPilot High Level Synthesis package developed at UCLA, which was licensed to AutoESL Design Technologies, Inc. Aplus was acquired by Magma in 2003, and AutoESL was acquired by Xilinx in 2011.

 
 
 
 

 

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