专用集成电路与系统国家重点实验室
讲座信息

题  目:A Fully-parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-throughput Applications
报告人:Yeong-Luh Ueng(National Tsing Hua University, Hsinchu, Taiwan)
时  间:2014年10月13日(周一)上午9:00-11:00
地  点:张江校区微电子楼389室

Abstract
Low-density parity-check (LDPC) codes have been adopted in many communication systems. For optical communications, high-through LDPC decoders are required, where a fully-parallel decoder architecture is usually required. In this talk, we will present a normalized probabilistic min-sum algorithm for LDPC codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz, achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance. 

Biography
Yeong-Luh Ueng received the Ph.D. degree in communication engineering from the National Taiwan University, Taipei, Taiwan, in 2001. From 2001 to 2005, he was with a private communication technology company, where he focused on the design and development of various wireless chips. Since December 2005, he has been a member of the faculty of the National Tsing Hua University, Hsinchu, Taiwan, where he is currently an Associate Professor with the Department of Electrical Engineering and the Institute of Communications Engineering. His research interests include coding theory, wireless communications, and communication ICs. He has published 22 IEEE journal papers including 20 full papers. He also has presented 18 technical contributions related to the IEEE 802.16 standard. He was also invited to speak at the 6th International Symposium on Turbo Codes & Iterative Information Processing, one of the most well-known symposiums in the area of error correction coding. He was elected as an honorary member of the Phi Tau Phi Scholastic Honor Society. He also earned the Excellent Industry-Academia Collaboration Award, National Tsing-Hua University, in 2013 and 2014.

 
 
 
 

 

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