专用集成电路与系统国家重点实验室
系列讲座之十


题  目:Assertion Synthesis – Finding Bugs by Mining Simulation Data?
报告人:
Dr. Yunshan Zhu (Atrenta VP)
时  间:2012年9月6日(周四)上午10:00-11:00
地  点:张江校区微电子楼369室

Abstract:
Functional verification is widely regarded as the bottleneck in the design of complex SoCs. Regardless of the speed of a simulator or formal engine, the verification result is only as good as the design specification. Without an adequate executable specification, the design and verification team will risk chip failures that cause re-spins and schedule overruns and suffer from long debugging turnaround time.
Assertion synthesis analyzes a large amount of simulation data to automatically generate assertions and functional coverage properties. The assertions and coverage properties serve as executable specification for RTL design and functional verification, allowing design and verification teams to catch corner case bugs, expose functional coverage holes, and increase verification observability.
This talk introduces the concept of assertion synthesis and demonstrates how the technology has been applied to verify complex industrial SoC designs.

Bio:
Dr. Yunshan Zhu is VP of New Technologies at Atrenta. Prior to Atrenta, Dr. Zhu co-founded NextOp Software Inc. He was the CEO of NextOp until its successful acquisition by Atrenta. At NextOp, Dr. Zhu co-invented the assertion synthesis technology, which is in production use at many leading semiconductor companies. Dr. Zhu worked as a researcher in formal verification at Synopsys Advanced Technology Group. Dr. Zhu was also visiting scientist and a post-doc at Carnegie Mellon University where he co-invented the bounded model checking algorithm. Dr. Zhu did his undergraduate study at University of Science and Technology of China and received his Ph.D. in Computer Science from University of North Carolina at Chapel Hill.

 
 
 
 

 

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