专用集成电路与系统国家重点实验室
系列讲座之二

题  目:Yield Enhancement for 3D-stacked ICs: Recent Advances and Challenges
报告人:Prof. Qiang Xu (Chinese University of Hong Kong)
时  间:2012年3月19日周一下午13:30-14:30
地  点:张江校区微电子楼369室

Abstract
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the "known good die" problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this talk, we survey recent advances in this filed and point out challenges to be resolved in the future.

Biography
Qiang Xu is an associate professor of computer science & engineering at the Chinese University of Hong Kong. He leads the CUhk REliable computing laboratory (CURE Lab.) and his research interests include fault-tolerant computing, trusted computing and hardware-accelerated computing. He has published 80+ papers in referred journals and conferences, including 1 best paper and 4 best paper candidates at prestigious conferences such as ICCAD and DATE. He is currently serving as an associate editor for IEEE Design & Test of Computers.

 
 
 
 

 

Copyright© 2003-2018 复旦大学微电子学院
联系我们