专用集成电路与系统国家重点实验室
系列讲座之十二

 

题  目:集成电路可靠性设计
时  间:2011年11月10日(周四)下午14:00-15:30
地  点:张江校区微电子楼389

Prof. Bharat Bhuva (Vanderbilt University, USA, the director of Graduate Studies)
Abstract: For ICs fabricated in deep sub-micron technologies, major reliability challenges are soft errors and process-parameter variations. This talk will focus on soft errors for 40 and 28 nm technologies. Starting with root causes of soft errors, the talk will examine masking factors, transients, upsets, simulation, and mitigation approaches for CMOS technologies. This talk will also focus on areas for research collaboration and student exchange. Vanderbilt University research areas and capabilities for design, simulation, and testing will also be discussed.
Bio: After completing his graduate work at North Carolina State University, Dr. BharatBhuva has been with Vanderbilt University for the past 25 years. During 1993-1999, he was Associate Director of a six university consortium focused on research for electronics in space environments. Currently, he is the director of graduate studies and a Fellow of the Institute of Space and Defense Electronics. Dr. Bhuva’s current research focus has been on soft errors on advanced technologies. He has also worked on inter- and intra-chip optical interconnects to alleviate limitations of metal interconnects, and bio-electronics that combines advances in biology and electronics. He has designed ICs at each of the technology node starting from 1.5 um to 28 nm to investigate multiple reliability challenges. He has also been instrumental in developing test methodologies and CAD tools related to these reliability challenges. He haspublished and presented over 350 papers and presentations.

Prof. Li Chen (University of Saskatchewan, Canada, the director of the VLSI laboratory in the Department of Electrical and Computer Engineering)
Abstract: The presentation will be around 35-40 minutes. The University of Saskatchewan and City of Saskatoon will be briefly introduced at the beginning of the talk. Then more detailed information will be provided about the research projects, capabilities and research resources of Dr. Chen’s research group. The research group has been working on the projects such as radiation- and fault-tolerant microelectronics since 2006. The group has access to a broad range of EDA tools for designing integrated circuits using advanced silicon and GaAs technologies. The research group is also developing a pulsed laser testing center which is capable to perform one-phone and two-photon testing on microelectronics. Dr. Chen has received funds from National Science and Engineering Research Council of Canada (NSERC), Canadian Foundation for Innovation (CFI), NASA, Cisco Systems Inc. and Intersil Inc.
Bio: Li Chen received the B.S degree from Tianjin University, Tianjin, China in 1991, and M.Eng and Ph.D. degree from University of Alberta, Edmonton, Canada in 2000 and 2004, respectively. Dr. Chen has been the faculty member of the Department of Electrical and Computer Engineering, University of Saskatchewan since 2006, where he is endowed with the Barbhold Chair Professor in Information Technology. He was promoted to Associate Professor in July 1, 2011. His research interests are in radiation- and fault-tolerant microelectronics, ultra low-power microelectronics, ultra wideband biomedical sensors and systems. He is the director of the VLSI laboratory in the Department of Electrical and Computer Engineering, University of Saskatchewan. Dr. Chen received NSERC SPG award in 2008, and CFI Leader’s Opportunity Fund Award in 2009. He has 50 publications in referred journals and conferences proceedings.

Dr. Shi-jie Wen (Premier Engineer, Cisco, USA, Fellow of Cisco Research Center)
Abstract: I’ll provide a talk titled on "Cross layer reliability towards self healing". In this talk, I’ll talk about how we ensure and handle the system level reliability. What is the ultimate goal and what are common practice we are using today.
Bio: Shi-Jie Wen received his Ph.D in Material Engineering from University of Bordeaux I in 1992. He joined Cisco Systems Inc., San Jose, CA in 2004, where he has been engaged in Si process and IC component technology reliability, qualification and quality assurance. His main interests are in SEU, WLR, complex failure analysis, etc. Before Cisco, he worked in Cypress Semiconductor where he was involved in the area of product reliability and qualification with technology in 0.35u, 0.25u, 0.18u, 0.13u and 90nm. He has been authoring or co-authoring more than 100 papers in journals or conference.

 
 
 
 

 

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