专用集成电路与系统国家重点实验室
系列讲座之十

题  目:THERMAL-ELECTRICAL AND MECHANICAL INDUCED MIGRATION SIMULATION of INTERCONNECTS, VIAS PoP, μBGA AND TSV
报告人:Prof. Kirsten Weide-Zaage (Universität Hannover in Germany)
时  间:2011年10月24日下午2:00-2:45
地  点:张江校区微电子楼369

Abstract
Modern metallization systems down below ULSI are more and more sensitive against influences of geometrical and material changes in consideration on the mechanical stress and electrical mechanical behavior. The reliability of these metallization systems is influenced by these changes. The determination of the reliability of such metallization systems is done by thermal and thermal-electrical accelerated stress tests under high temperature load. The degradation due to electro-, thermo- and stress migration is one major concern in reliability investigations. Measurements are time consuming and expensive. A help can be the prediction of local weak spots by finite element simulations. As a concrete example the degradation phenomena in dual damascene copper (DD-Cu) metallizations under high current density and high substrate temperature conditions will be investigated by finite element modeling and calculations of the mass flux and its divergence. The consideration of process induced stress instead of a stress free temperature of the metallization is important. Variations of the via geometry and barrier or dielectric materials as well as boundary conditions influences the reliability of the investigated system.
New package generations have to offer a rising amount of solder contacts or they are exposed to extreme operation conditions. Cracking as a consequence of coefficient of thermal expansion (CTE) mismatch is one well known risk concerning the reliability of solder joints. Modern 3D-Packing leads to an increased number of ICs on the same amount of space, due to this the contact density increases and the diameter of the solder joints decrease. CoC as a possibility for 3D integration can be used for the vertical assemble of ICs. CoC structures base on a direct connection of ICs on chip level with through silicon vias (TSVs) and micro bump arrays (μBGAs) with new reliability aspects. The shrinking dimensions of solder joints and the rising operation temperatures cause new risks to the reliability of solder joints. Two new phenomena are void formation and accelerated inter metallic compound (IMC) growth due to electromigration (EM). During the development of a reliable micro electronic system, migration induced reliability issues have to be considered on chip and package level. To explore the electromigration phenomena stress tests with different boundary conditions were performed. As example the average lifetime of different Package-on-Package (PoP) structures was determined and failure analyses were made. Electro-thermal and thermal-mechanical simulations were performed. The simulation results enabled a more detailed interpretation of the stress test results. Based on validated simulation results the stress on PoP, μBGA and TSV structures at different operation condition were investigated. A current ramp was calculated to predict the EM performance of future solder joints and copper traces in PoP, μBGA and TSV.

Biography
Kirsten Weide-Zaage is Privatdozent and Projectleader in the Department Semiconductor Technology and Robust Electronic at the Information Technology Laboratory of the Gottfried Wilhelm Leibniz Universität Hannover in Germany. She got her Diploma as Physicist of the University of Hannover in 1988 and the Doctor Thesis in Electrical Engineering of the University of Hannover in 1994. In March 2011 she got the Habilitation in Microelectronics of the Leibniz Universität Hannover. The activities of Kirsten Weide-Zaage are Project Management and Procurement, Industrial Research and Supervising.
Her Scientific Research Topics are: Reliability, High Temperature Applications, Layout Optimization, new Packaging Concepts and Nanoelectronics. She has more than 50 specific Publications in that field.

 
 
 
 

 

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