专用集成电路与系统国家重点实验室
系列讲座之八

题  目:Many-Core Computational Arrays for Efficient and High-Performance DSP, Multimedia, and Embedded Processing
报告人:Bevan Baas (University of California, Davis)
时  间:2011年10月8日上午10:00-11:00
地  点:张江校区微电子楼389

Abstract
The Asynchronous Array of Simple Processors (AsAP) is a programmable and reconfigurable processing system that: enables high throughput and high energy-efficiency, is well matched to workloads containing many varied DSP tasks, and is well suited for deep submicron VLSI fabrication technologies.
AsAP is composed of a large number of programmable reduced-complexity processing elements with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS). Oscillators fully halt when there is no work to do, and restart at full speed in less than one cycle after work becomes available. Processors communicate through a reconfigurable full-rate modified 2-D mesh network.
A chip containing 36 610 MHz programmable processors was fabricated in 0.18 um CMOS and is fully functional. [ISSCC06]
A second generation 65 nm CMOS design contains 167 processors and has many new architectural features including dedicated FFT, Viterbi, and video motion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect. The programmable processors are able to individually and dynamically change their clock frequency and supply voltage (choosing among VddHi, VddLo, or disconnected). The chip is fully-functional with measurements showing the programmable processors operating up to 1.2 GHz at 1.3 V. At 1.2 V, they operate at 1.07 GHz and 47 mW when 100% active. At 0.675 V, they operate at 66 MHz and dissipate only 608 uW when 100% active. Due to the MIMD architecture and oscillator halting, the system operates with an energy per ALU or MAC operation of 9.2 W at 1 Tera-op/sec virtually independent of the system load. [SympVLSI08,JSSC09]
Several dozen DSP and general tasks have been coded plus more complex applications including: JPEG encoders, AES encryption engines, a full-rate 1080p 30fps HDTV residual encoder, a fully-compliant IEEE 802.11a/11g Wi-Fi wireless LAN baseband transmitter and receiver, a complete first-pass H.264 encoder, and a large portion of the mid- and back-end processing for a medical ultrasound unit. Power, throughput, and area results compare very well with solutions on existing programmable DSP processors. A recent project has applied the processor arrays to enterprise workloads as co-processors and functional units and has achieved promising results. A simple C compiler and automatic mapping tool greatly simplify programming.

Biography
Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now an Associate Professor.
Dr. Baas' research interests are in the algorithms, architectures, circuits, and VLSI for high-performance, energy-efficient, and area-efficient computation with strong consideration of the challenges and opportunities of future fabrication technologies. He is interested in both programmable and special-purpose processors with an emphasis on DSP, multimedia, embedded, and other workloads.
Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, and the Most Promising Engineer/Scientist Award by AISES in 2006. Since 2007 has has been an Associate Editor for the IEEE Journal of Solid-State Circuits. He has served and is serving as: Program Committee Co-Chair of the IEEE HotChips Symposium on High-Performance Chips in 2011 and Program Committee member in 2009-10; Parallel Architecture Co-Chair of the 2011 Design Automation Conference (DAC) Workshop on Parallel Algorithms, Programming, and Architectures; Technical Program Committee member of the International Conference on Computer Design (ICCD) 2004-05, 2007-09; Technical Program Committee member of the IEEE International Symposium on Asynchronous Circuits and Systems in 2010; International Solid-State Circuits Conference (ISSCC) Student Research Preview Committee member in 2012; and the Technical Advisory Board of an early stage technology company.

 
 
 
 

 

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