专用集成电路与系统国家重点实验室
系列讲座之四

题  目:Improving Runtime and Memory Requirements in EDA Applications
报告人:Alan Mishchenko (UC Berkeley, USA)
时  间:2011年5月11日(周三)下午1:30-2:30
地  点:张江校区微电子楼269

Abstract
This talk summarizes the 10-year experience of developing computationally efficient solutions for problems in logic synthesis and formal verification. Implementation of network data-structure, satisfiability solver, And-Inverter Graph (AIG) package, and Binary Decision Diagram (BDD) package are discussed. Special attention is given to memory management that reduces CPU cache misses. Implementations are illustrated using public-domain code in ABC, a logic synthesis and verification system developed at UC Berkeley.

Biography
Alan Mishchenko graduated from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. From 1998 to 2002 he was an Intel-sponsored researcher at Portland State University. In 2002, he joined the EECS Department at UC Berkeley, where he is currently an associate researcher at Berkeley Verification and Synthesis Research Center (BVSRC). Alan is interested in developing efficient algorithms for synthesis and verification.

 
 
 
 

 

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