前沿讲座通知

演讲人:Jacques Rouillard, PhD
         École des Mines de St Étienne(法国高矿大学)
时  间:2010年11月24日下午1 :30——3 :30
地  点:张江校区微电子楼369会议室

Abstract :

 

VHDL : Involved in the IEEE VHDL’93 standardization under the auspices of the european ECIP project. Was awarded a recognition certificate of the IEEE for this task.

Co-Founder of LEDA, a CAD company dedicated to the developpement of VHDL and Verilog front-ends, then sold to Synopsys.

 

Reference Books

  • VHDL Designer's Reference - coauthor - 0-7923-1756-4
  • VHDL'92 - coauthor - 978-0792393566
  • Coeditor of CIEM (Current Issues in Electronic Modeling) : twelve books - ISBN 978-0792398745 and others.

 

Short Bio of the Lecuturer :

Resarch engineer in CNET (France-Telecom R&D)

Responsible for a task in the European ECIP project

Head of Dpt at ESIM (school of engineering, Marseille)

Various teaching & administrative positions within ESIM, ISMEA then ISMIN (école des Mines de St étienne)

 

VHDL-AMS seminar, presented by Jacques Rouillard (5-6hours)

This seminar presents VHDL-AMS 1076.1, a superset of VHDL 1076. It goes through concepts and constructs of both, and explains interactions between the two simulation kernels.

Goal : the seminar gives a picture of the solutions provided by VHDL-AMS to the analog and mixed-mode designer.

Prerequisites : the attendee should have a reasonnable academic knowlegde of one hardware description language (Verilog or VHDL) and an interest in mixed-mode simulation kernels.

  • VHDL : presentation, history, related standards
  • Objects in VHDL : types, variables, signals,…
  • Active statements in VHDL (assignment, process..)
  • Event-Driven simulation : the simulation cycle in VHDL.
  • Objects in VHDL-AMS : natures, quantities, terminals
  • Active statements in VHDL-AMS (equation, procedural)
  • Analog simulation : the simulation cycle in VHDL-AMS.
  • Interactions Analog/Events : break, ABOVE
  • Hierarchy in VHDL and VHDL-AMS : entities, architectures, components, ports.
  • Hierarchy-related statements in VHDL and VHDL-AMS : instantiations, configurations, maps.
  • Short examples (for each topic)

 

 
 
 
 

 

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