讲座信息

Statistical Timing: Where’s the Tofu?

 

When: 2010/8/9 (Monday) 9:30am11:00am
Location: Room 389, Microelectronic Building, Zhangjiang Campus

Abstract:
For over 6 years, there have been numerous papers on the topic of Statistical Static Timing Analysis (SSTA), and several product offerings. But does it really work in practice? What are the benefits of statistical sign-off? What are the pitfalls? How does one optimize towards statistical sign-off? As we transition to 32 and 22 nm, is multi-corner timing running out of steam? Are we marginalizing our business by margining? Our industry is at a crucial juncture at which these questions must be answered.
This talk will use real timing data from several industrial 65 nm ASICs to answer these questions. Real timing data will be used to compare and contrast four timing methodologies: two-corner timing, multi-corner timing, exhaustive corner timing and SSTA. The value-add, pessimism incurred and concomitant margining in each of these flows will be spelled out with supporting data.

Speaker: Chandu Visweswariah
Affiliation: IBM Systems and Technology Group, Hopewell Junction, NY
Chandu Visweswariah received a PhD in Computer Engineering from Carnegie Mellon University in 1989. From 1989 to mid-2009, he was a Research Staff Member at the IBM Thomas J. Watson Research Center in Yorktown Heights, NY, where he headed the Circuit and Interconnect Analysis group. He is presently Senior Manager of Timing and Circuit Analysis in the Systems and Technology Group at East Fishkill, NY. Chandu is an IBM Distinguished Engineer and a Fellow of the IEEE.

Speaker: Jinjun Xiong
Affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Jinjun received his PhD in Electrical Engineering from UCLA in 2006, and since then has been a Research Staff Member at the IBM Thomas J. Watson Research Center in Yorktown Heights, NY, working on statistical timing and its application to at-speed test. Jinjun won an Outstanding PhD Student Award and two Best Paper awards. In addition, his research has garnered 5 Best Paper nominations. His research interests include design automation for VLSI circuits and systems, large scale optimization and combinatorial mathematics.

 
 
 
 

 

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