數字電路的邏輯換線轉換技術, 算法, 與應用

Applications, Algorithms, and Techniques for Digital Logic Rewiring Synthesis

 

Speaker: Yu-Liang (David) Wu (Chinese University of Hong Kong)
When:     2010/7/13 (Tue) 10:00am
Location: Room 369, Microelectronic Building, Zhangjiang Campus

Abstract:
Without the help of compilers, no big software can be implemented. Similarly, without the help of VLSI CAD (EDA) tools, there will be no modern high-performance electronic chips. In electronics, logic synthesis is an EDA process by which an RTL or Boolean expression is transformed into an equivalent better (or optimized) form. (K-map can be considered the first textbook logic synthesis technique a digital circuit designer learns.)
Rewiring is a new kind of logic synthesis technique developed in recent 20 years and particularly powerful and flexible for interconnect-sensitive EDA applications, ranging from circuit partitioning, Place&Route, low power, .. etc. for both ASIC and FPGA designs. One of the most mature rewiring techniques is the ATPG based Redundancy Addition and Removal (RAR) which adds a redundant alternative wire to make an originally non-redundant target wire become redundant and thus removable. In this introductory talk, we will introduce a few rewiring applications, give the basic mechanisms worked behind RAR rewiring techniques and also introduce a most recently developed so-called Error Cancellation based Rewiring scheme (ECR, DAC2010) which can also do non-RAR based rewiring operations with high efficiency. (In the past, our related work has received VLSI’00 Honorable Mention Award, SPL’07 Best Paper Award, IPS’07 Best Presentation Award, and US pending patents USA61/031,268 and USA61/058,142).

Biography of the speaker:
Prof. Yu-Liang (David) Wu (ylw@cse.cuhk.edu.hk) received his Ph.D. degree in Electrical and Computer Engineering from University of California at Santa Barbara in 1994. On 1985, he worked in Internet Systems Corporation on network communication protocols. From 1986 to 1988, he worked at AT&T Bell Labs for telephone operation systems. From 1988 to 1989, he worked for Amdahl Corporation on tester software designs for super-computers. From 1994 to 1995, he worked at Cadence on the silicon synthesis product (PBS). Prof. Wu joined the Computer Science and Engineering Department of the Chinese University of Hong Kong (香港中文大學) since 1996. His current research interests mainly relate to EDA (VLSI CAD) optimization for VLSI circuit designs.

 
 
 
 

 

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