前沿讲座通知
The Semiconductor Technology Roadmap: Miniaturization and Diversification


时  间:2010年3月18日上午10:00 - 11:00
地  点:邯郸校区微电子楼B213会议室
演讲人:Mart Graef博士,荷兰Delft理工大学

Abstract:
For more than thirty years, the microelectronics industry has been driven by the fact that the density of functions in an integrated circuit could be increased, while the cost per function could be reduced. This phenomenon, known as “Moore’s Law”, has served as the basis of the international technology roadmap for semiconductors (ITRS). Its focus over time has been the miniaturization of the electronic components (transistors), enabled by continuous innovations in process technology end device architectures. CMOS became the standard technology for digital memory and logic devices.
At the same time, the “end of the roadmap” has always seemed to be close at hand, due to the perceived physical limitations as well as economic constraints.
During the last few years, a new trend is gaining ground. The semiconductor technology roadmap is no longer guided exclusively by the scaling of CMOS-based components. Increasingly, new non-digital functionalities are being integrated into microsystems, thus adding a new dimension, which may be labeled “multifunctionality” to the roadmap. This trend has become known under the term “More than Moore”.
In the presentation, an account will be given of the semiconductor technology roapmapping process, its past, present and future. In particular, attention will be given to the challenges and opportunities offered by the “More than Moore” domain, which is waiting to be explored.

About the speaker:
Mart Graef is a strategic program manager at the Delft Institute of Microsystems and Nanoelectronics (DIMES) at the Technical University of Delft. He is involved in various technology partnerships, mostly within the framework of European cooperative projects. He is a member of the International Roadmap Committee, which guides the creation of the International Technology Roadmap for Semiconductors (ITRS).
Mart Graef received a PhD in Solid State Chemistry from the University of Nijmegen, the Netherlands in 1980. Subsequently, he joined Philips Research, where he held various positions in Eindhoven (the Netherlands) and Sunnyvale (USA) as a scientist and manager in the field of semiconductor process technology. Later, he joined Philips Semiconductors and NXP as a strategic program manager. Assignments included the coordination of European cooperative projects, such as the Joint Logic Project, and chairing the Lithography Program Advisory Group at Sematech. He was a member of the Technology Steering Group of MEDEA+ and CATRENE (Eureka), and participated in the creation of the Strategic Research Agendas for ENIAC (European Nanoelectronics Initiative Advisory Council) and Point-One (Pole of Innovation in Advanced Technologies).

 
 
 
 

 

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