学术报告:Nano-Structured Materials for
Nano- and Macro-electronics - Challenges and Opportunities

 

时  间:2010年1月4日下午3:00-5:00;

地  点:邯郸校区微电子学楼B213会议室

演讲人:张世理

This presentation will focus on the research on carbon nanotubes (CNT) conducted at KTH/UU over the past 7 years. I will start the presentation by motivating the CNT research from the trends and needs in aggressive downscaling of CMOS technology. It will become clear why a quasi 1-D structure that CNTs assume is so attractive as the building block for the extremely downscaled devices. Tremendous efforts have been devoted to CNT-based nanoelectronics since the first demonstration of CNT filed-effect transistors in 1998. However, two grand challenges have severely hindered the progress of CNT nanoelectronics: (1) existing synthetic methods always produce mixed CNTs with about 33% metallic CNTs and 67% semiconducting CNTs, (2) techniques need to be developed for site-selective placement of CNTs with desired quantities and orientation. Fault-tolerant circuitry is a new direction being actively pursued to address both difficulties. A different domain to research on is CNT-based macroelectonics where large-area and low-cost electronics with medium performance find applications in a wide range of areas. With various printing techniques available, this field of macroelectronics has attracted an increasing interest over the past several year. I will give many details about how we have pursued this part of the research with theory and practice, and where we see the challenges and opportunities.

 

 
 
 

 

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