Gate Dielectric Reliability:

Experiments and Theories


Ernest Y. Wu


Semiconductor Research and Development Center
IBM System and Technology Group, USA


Over last decade, the aggressive scaling in microelectronics for higher performance and density has maintained an unprecedented pace and has pushed miniaturization of device dimension and isolation to nearly atomic limit. Nowadays, oxide thickness has first reached to an atomic scale of ~10 Å with only a few atoms in advanced technology nodes. The requirement of high reliability for ultra-thin dielectric films is one of most challenging and active research areas. This challenge has stimulated much research and led to new physical understanding of defect generation and oxide breakdown process and the development of new reliability projection model and methodologies. In this talk, we will first discuss breakdown statistics and the role of oxide thickness scaling in the framework of the percolation model of oxide breakdown. We will review the development of new voltage acceleration model, relating it to the physical models of oxide degradation. Particular emphasis will be given to the hydrogen release model that provides a feasible theoretical basis to the nowadays widely accepted power-law voltage acceleration model. Finally, we will provide an overview of current understanding on traps considered to be potentially responsible for oxide breakdown.


Ernest Y. Wu is a senior technical staff member in Technology Reliability Department at Semiconductor Research and Development Center (SRDC) in IBM System and Technology Group. He received M.S. and Ph.D. degrees in physics from University of Kansas in 1986 and 1989, respectively. After initially working in IBM Rochester site in Minnesota, Dr. Wu joined IBM Microelectronics Division in 1994 at Essex Junction, Vermont. He is responsible for technology qualification and development of physics-based reliability methodologies for dielectric breakdown. Dr. Wu has served on the device dielectric committee as chair and co-chair for 2007 and 2005 International Reliability Physics Symposium (IRPS), respectively. He is a member of CMOS and Interconnect Reliability committee of International Electron Device Meeting (IEDM) for 1999 and 2000. He has authored and co-authored more than 100 papers in technical journals and international conferences with several invited papers and tutorials as well as eleven IEDM papers. He has co-authored two books on gate dielectric reliability entitled “Reliability Wearout Mechanisms in Advanced CMOS Technologies” and “Defects in Microelectronic Materials and Devices”. In 2004, he received IBM Outstanding Technical Achievement Award for his contribution to ultra-thin gate reliability in advanced CMOS technology. His research interests include dielectric reliability physics, device physics and simulation, circuit reliability, and carrier injection and transport physics.



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