前沿讲座
Low Power Electronic Devices for SoC

时  间:2009年7月7日14:00-15:00
地  点:邯郸校区物理楼138会议室
演讲人:Albert Chin,Dept. of Electronics Eng., National Chiao-Tung University, Hsinchu, 300, Taiwan

Abstract:

Currently the IC chips consume a large amount of global energy and will continue to increase. This is even worse as the rapid down-scaling VLSI technology with higher IC density. It is urgently needed to lower the IC power consumption, in addition to build up more energy harvesting device.
In highly scaled ICs, the transistor leakage current becomes dominant for power consumption. This is due to the using ultra-thin ~1 nm gate oxide for MOSFET, but such thin SiON is required to achieve high drive current and fast circuit speed. To address this issue, we pioneered the high-k gate dielectric research more than a decade ago. The high-k CMOS transistors have been used for Intel’s 45 nm node IC chips starting at 2007, to lower down DC power dissipation. Our pioneered Al2O3 and La2O3 high-k gate dielectrics have been used with HfSiON to reach low Vt 32~22 nm node p- and n-MOSFETs for high-performance low-power ICs. The high-k La2O3 also has the lowest leakage current for MOSFET with EOT<1 nm, among metal-oxides in the Periodic Table.
Besides logic CMOS, fast-speed DRAM and non-volatile memory (NVM) are also required. To address power consumption in DRAM, we developed the very high-k SrTiO3 that fits well with the Samsung’s roadmap. Such very high-k dielectric increases the DRAM capacitance and charge storage (Q=CV), allowing low voltage and low power (P=IV) operation. The current flash NVM consumes power from needed high voltage operation and charge-pumping circuit. Using high-k technology, we have achieved fast 100 ms speed and very low write voltage of 8~9 V that further decreases to half using an inverter circuit. This is the fist demonstration of NVM device operating under 5V without power dissipating charge-pumping circuit. Our high-k trapping NVM is listed in the Intl. Technology Roadmap for Semiconductors (ITRS) and confirmed by Samsung.
Communication function is needed for SoC. The power consumption of Si-based RF IC is mainly in the low Q passive devices and poor power transistors. We developed a simple process to improve the power loss for devices on VLSI-standard Si wafer. High performance RF inductors, filters and antennas on Si operating up to 100 GHz were realized for the first time. We also invented the asymmetric-LDD transistor with record best RF power performance among Si MOSFET. The AC power consumption is another limit for high frequency RF ICs. Large AC power consumption improvement is reached by us using the basic physics of CV2f and demonstrated in a 3D IC. Such fast 3D IC can decrease the performance gap compared with bio-system.

 

Bio:

Albert Chin (SM’94) received the Ph.D. from the Department of Electrical Engineering, University of Michigan, Ann Arbor, in 1989.
He was with AT&T-Bell Labs from 1989 to 1990, General Electric-Electronic Lab from 1990 to 1992, and visited the Texas Instruments’ Semiconductor Process & Device Center from 1996 to 1997. He is a Professor with the National Chiao Tung University, Taiwan ROC, and a visiting Professor at the Si Nano Device Lab, National University of Singapore from 2002~2005. He is a pioneer in high-k gate dielectric and metal-gate research (Al2O3, La2O3, LaAlO3, HfLaON), which result in largely improved DC leakage current in MOSFET. His pioneered Al2O3 and La2O3 have been used with HfSiON to lower down the Vt of 32~22 nm node p- and n-MOSFETs. He invented the Ge-On-Insulator (GOI) CMOS to enhance the mobility, 3-D ICs to solve the AC power consumption and to extend the VLSI scaling, resonant cavity photo-detector for high gain-bandwidth product, and high mobility strain-compensated HEMT. He is a leader for high-k trapping layer (AlGaN and HfON) SONOS memory and charge-trapping-engineered flash (CTEF). He initiated the nano-crystallized very high-k SrTiO3 MIM capacitors used for analog/RF and DRAM. He made significant contributions to high performance RF inductors, filters and antennas on Si operating up to 100 GHz, by transforming the underlying substrate into semi-insulating using high-energy ion-implantation created deep traps. He also invented the asymmetric-LDD MOSFET with record high RF power performance. He has published more than 300 technical papers and presentations, where 8 co-authored papers in high-k area are recorded as Highly Cited Papers (top 1% citation of Essential Science Indicators). His high-k, GOI, non-volatile memory, MIM capacitor and RF devices were cited and listed in the Intl. Technology Roadmap for Semiconductors (ITRS). He has given invited talks at the IEEE Intl. Electron Devices Meeting (IEDM) and other conferences in the US, Europe, Japan, Korea (i.e., Samsung Electronics) etc and served as rump section panelist in 62nd Device Research Conference. His research interests include quantum-trap flash memory, solar cells, high density MIM DRAM capacitors, RF Si device, metal-gate/high-k nano-CMOS and circuit design.

Dr. Chin serves as Distinguished Lecturer of IEEE Electron Device Society the deputy director of Nano-electronics Consortium of Taiwan. He was also a Subcommittee Chair (2008) and is currently the Asian Arrangements Co-Chair of IEDM.

 

 
 
 
 

 

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