专用集成电路与系统国家重点实验室
系列讲座


题  目:Clocking in High Performance and Low Power SoC Design
报告人:Dr. Xiaodong Yang
时  间:2009年5月15日(周三)上午9:30-10:30
地  点:张江校区微电子楼389

Abstract
Clocking is emerging as a critical design issue in high performance and low power SoC designs, which involves many design aspects such as logic design, circuit design, physical implementation, timing analysis and verification etc. This talk is trying to provide an overview on modern SoC clocking design from a practical perspective with recent research highlights. We will discuss topics such as SoC clock management system design, high speed clock design techniques, low power clock design techniques, MCMM (Multiple-Corner-Multi-Mode) clock synthesis and CDC (clock Domain Crossing) checking, glitch-free multiplexing etc.

Biography
Xiaodong Yang, Ph.D
Dr. Yang received the B.E degree in Dept. of Electronic Engineering (major in Microelectronics), Tsinghua University in 1995. He received the Ph.D degree in Electrical and Computer Engineering from University of California, San Diego in 2000.
Dr. Yang joined Sun Microsystems in 2000 and worked on several microproessor design projects ( UltraSparcIII+, UltraSparcV, UltraSparcV). He was the leading circuit design engineer delivering Sun's first 2GHZ, 90nm, dula-core UltraSparcV microprocessor in 2003. He also developed some in-house CAD tools such as interconnect modeling, RC reduction, delay calculation and fast circuit simulation engine etc. Dr. Yang joined Synopsys in 2004 as a sernior R&D staff engineer in physical implementation group working on clock tree synthesis. In 2005, he served as the vice president of R&D in ICScape Inc, an EDA start-up located in silicon valley, California, leading the R&D effort in SoC clock analysis/optimization and timing optimization products with successfully applications in more than 30 SoC designs.
Dr. Yang has 2 US patens and a few pending. He published more than 10 technical papers in major IEEE conference and journals. Dr. Yang’s research interest is mainly in high performance and low power SoC circuit design and optimization techniques, timing analysis, circuit simulation, interconnect modeling and AMS verification methodology etc.

 
 
 
 

 

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