专用集成电路与系统国家重点实验室
系列讲座


题  目:NBTI Modeling, Simulation and Prediction from Transistor Level to SOC Register Transfer Level
报告人:杨胜齐 教授 上海大学
时  间:2009年4月23日(周四)上午10:00-11:00
地  点:张江校区微电子楼389

Abstract:
The rapid scaling of CMOS technology has resulted in new reliability concerns, such as Negative Bias Temperature Instability (NBTI). It primarily affects PMOS devices and may result in up to 50mV shifts in the threshold voltage (Vth) through the life time, translating to more than 20% degradation in circuit speed or in extreme cases to a functional failure. NBTI already became the dominant factor to limit circuit life time in 65nm technology node and below. Even tremendous efforts have been spent to improve the fabrication process, the impact of NBTI on circuit performance becomes so severe that technology improvement alone is not sufficient, especially after the introduction of high-k gate dielectrics in 45nm technology node. For nanoscale CMOS circuits, it is essential to develop design methods to understand, simulate, predict and minimize the degradation of circuit performance in the presence of NBTI in order to ensure reliable circuit operation over a desired period of time.

The analysis of NBTI is inherently more complicated than that of other traditional reliability issues, such as the hot carrier effect. NBTI exhibits a unique property of both stress and recovery behavior during circuit dynamic operation. Based on several works done with Dr. Wenping Wang and Professor Yu Kevin Cao in ASU and a recent NSF proposal, this talk will elaborate a unique methodology on how to model NBTI effect, more importantly, how to simulate, emulate, and predict the circuit timing degradation, further tracking the hot spots under NBTI effect from transistor level to SOC register transfer level. Besides NBTI, we will talk about some interesting chip design projects going on in SOC R&D Center at Shanghai University.

Speaker Information:

Shengqi Yang received the B.S. degree (Mechanical Engineering Department), the Economic Double Major degree (China Economic Research Center), in 2000, and the M.S. degree (Institute of Microelectronics), in 2002, all from Peking University, Beijing, China. He got the Ph.D. degree from Electrical Engineering Department at Princeton University, Princeton, NJ, in 2006. His PhD thesis is low power VLSI system design with consideration of reliability and security. He joined Intel in March 2006 and served as a Senior SOC Architect in Digital Home Group and was responsible for Canmore SOC video architecture. Starting from April 2008, he worked for Intel Mobility Group and was responsible for Gen6 and Gen7 GPU media processing feature development. In 2009, he joined the SOC R&D Center in Communication and Information Engineering Department, Shanghai University and was selected as the Shanghai “Eastern Scholar” Professor. He has five Chinese Patents and six US pending patens. He has published around 30 papers in major IEEE conferences and Transactions. His research interests include multimedia MPSOC design, embedded system design, low-power and reliable VLSI design, power modeling and optimization, and CMOS compact modeling. He was a member of IEEE (just deactivated due to being busy with proposals and no time to take care).

 
 
 
 

 

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