前沿报告
A Talk on Strained Channel MOSFETs

报告人:Yi Zhao,School of Engineering, The University of Tokyo
时  间:2009年3月9日下午3点至5点
地  点:邯郸校区微电子楼B213会议室

 

Abstract:

Strain technology, which can enhance the channel mobility according to the modulation of the sub-band structures, has been recognized as a very important booster for CMOS (complementary metal-oxide semiconductor) technology beyond 90 nm node. Although there have been many theoretical and experimental investigations about the scattering in inversion layers of strained-Si(s-Si) n and pMOSFETs, the scattering mechanisms in s-Si, especially Coulomb scattering and surface roughness scattering, have not yet been well understood. High substrate impurity concentrations are required in CMOS under the future technology nodes, which makes Coulomb scattering and surface roughness more significant for short channel advanced MOSFETs. In this talk, I would like to introduce our new findings and physical understandings in terms of the Coulomb and surface roughness scatterings in inversion layers of strained n and pMOSFETs.

 

Bio:

Yi Zhao was born in Zhejiang, China, in 1977. He received the B.S. degree from Nanjing University of Astronautics and Aeronautics, Nanjing, China, in 2000, the M.S. degree from Zhejiang University, Hangzhou, China, in 2003, and the Ph.D. degree from The University of Tokyo, Tokyo, Japan, in 2007. His Ph.D. study was focused on lanthanum-based high-permittivity(k) gate dielectrics. From July 2003 to September 2007, he was with Shanghai Hua Hong NEC(HH-NEC), Shanghai, China, as a Research and Development Engineer, where he was engaged in the research and development on 0.25-, 0.18- and 0.13-μm CMOS processes, particularly in wafer-level reliability evaluation and test structure design. After finishing his Ph.D. study at The University of Tokyo, he was with the Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, as a Research Fellow for half a year. Since April 2008, he has been with the Department of Electrical Engineering and Information Systems, School of Engineering, The University of Tokyo, as a JSPS research Fellow, where he is currently working on the characterizations and physics of strained-Si MOS devices.

 
 
 
 

 

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