学术报告 High Performance Deep - Submicron Inversion - Mode InGaAs MOSFET
报告人:Yanqing Wu,Purdue University, USA 地 点:邯郸校区微电子学楼B213会议室 时 间:2009年3月9日上午9点30分
The continuous device scaling and performance improvements required by the International Technology Roadmap of Semiconductors are facing a grand challenge as conventional Si CMOS scaling comes to its fundamental physical limits. As several new technologies such as high-k metal gate integration, non-planar Si transistors, and strained channel materials have been developed to maintain the Moore’s Law, tremendous efforts have been spent to look into those alternative channel materials “beyond Si” such as germanium and III-V compound semiconductors. Benefiting from their high electron mobility and velocity, III-V High Electron Mobility Transistors (HEMTs) or Quantum Well Transistors with channels of In-rich InGaAs, InAs and InSb have been demonstrated with superior device metrics such as transconductance, cut-off frequency, and gate delay. However, the gate leakage of these transistors limits their applications in large scaled integrated circuits. In the quest for perfect dielectrics on III-V semiconductors, significant progress has been made recently on inversion-type enhancement-mode InGaAs NMOSFETs, operating under the same mechanism as Si MOSFETs, using high-k gate dielectrics. The promising dielectrics include ALD Al2O3 , HfO2 , HfAlO , ZrO2 and in-situ MBE Ga2O3(Gd2O3) . In this presentation, I will give a presentation of the most recently experimentally-demonstrated ALD high-k/In0.75Ga0.25As MOSFETs with gate length down to 100 nm and supply voltage as low as 0.8 V. Important scaling metrics such as On/off current ratio, sub-threshold swing, and drain-induced barrier lowering which are affected by short-channel effect will be discussed . Other device metrics, such as intrinsic gate delay and energy-delay product per unit width will also be presented and discussed for the potential digital applications.
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