前沿讲座

Title: Architecture-level Thermal Modeling and Simulation for
Chip-Multiprocessor Designs

Prof. Sheldon X-.D.Tan stan@ee.ucr.edu

Department of Electrical Engineering
University of California at Riverside
http://www.ee.ucr.edu/~stan

时间:2008年7月10日下午13:30-15:00
地点:张江校区微电子楼389教室

Abstract:

As CMOS technology is scaled into the nanometer region, the power density of high-performance microprocessors has increased drastically. The exponential power density increase will in turn lead to average chip temperature to raise rapidly. Higher temperature has significant adverse impacts on chip packing cost, performance and reliability. Excessive on-chip temperature leads to slower transistor speed, more leakage power consumption, higher interconnect resistance, and reduced reliability. Chip-multiprocessing techniques, where multiple CPU-cores and caches are integrated into a single chip, provide a viable solution to the temperature/power problems. But managing thermal effects in the multi-core microprocessors still remains a challenging problem.

In this talk, I will present the novel thermal modeling and analysis techniques at the chip architecture level, which were developed at the UCR mixed-signal nanometer research Lab (MSLAB), for potential run-time dynamic thermal management and designing more thermal-efficient multi-core microprocessors. We will first present moment matching based fast thermal analysis algorithm, called TMM and compare it with HotSpot-based thermal analysis method. We then present recently developed parameterized behavioral thermal modeling techniques at system and architecture level. A number of examples based on Intel quad-core microprocessors will be presented.

 

Bio of Dr. Sheldon X.-D. Tan

Dr. Tan is an Associate Professor in the Department of Electrical Engineering, University of California at Riverside. He received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999.

Dr. Tan has published intensively on various aspects of CAD for VLSI integrated circuits with 120+ peer-reviewed conference and journal publications. His research interests include modeling and simulation of analog/RF/mixed-signal and interconnect circuits, analysis and optimization of high performance power and clock distribution networks, architecture level thermal, power, modeling and simulation for multi-core microprocessors and embedded system designs based on FPGA platforms.

Dr. Tan is the recipient of National Science Foundation CAREER Award in 2004. He received a Best Paper Award from IEEE International Conference on Computer Design (ICCD’07), Best Paper Award Nomination from 2005 IEEE/ACM Design Automation Conference, Best Paper Award from 1999 IEEE/ACM Design Automation Conference. He also co-authored book Symbolic Analysis and Reduction of VLSI Circuits by Springer/Kluwer 2005 and Advanced Model Order Reduction Techniques for VLSI Designs, by Cambridge University Press 2007.
 
 
 
 

 

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