前沿讲座
Tutorial on Low-Power Digital Circuits

 

Part 1: Static and Dynamic Power Reduction
时间:2006年9月14日(周四)上午10:00–11:30

Part 2: Buses and Memories
时间:2006年9月15日(周五)上午10:00–11:30

地点:张江校区微电子楼389教室

Lecturer:Prof. Gerald E. Sobelman, Dept. of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (http://mountains.ece.umn.edu/~sobelman/)

Abstract:
This two-part tutorial will describe the mechanisms responsible for power dissipation in digital circuits and then present a range of low power design techniques. In this first part, we begin with a discussion of static power dissipation due to subthreshold leakage, gate leakage and band-to-band tunneling currents. A number of techniques for reducing static power will be presented including power gating, multiple threshold voltages, adaptive body biasing, multiple supply voltages, thick gate oxide devices and long channel devices.

This is followed by a discussion of the factors causing dynamic power dissipation. Several design techniques for minimizing dynamic power are described including low swing clocking and associated storage elements, double edge triggered flip-flops, clock gating, dynamic voltage scaling, and low-power pipelining.

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Gerald E. Sobelman is a faculty member in Electrical and Computer Engineering at the University of Minnesota. He does research in the areas of digital VLSI circuit and system design with applications in signal processing and communications. He has authored or co-authored more than 60 technical papers and 1 book, and he holds 10 U.S. patents. He has taught short courses on VLSI design and has consulted for several companies.

 
 

 

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