讲座信息:Semiconductor Design and Test Research: Scan Data Compression

 

时  间:6月21日(周三)下午1:30
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摘  要

An Introduction to Semiconductor Design and Test Research: Scan Data Compression Dr. Ir. Erik H. Volkerink

Abstract:
Because the semiconductor manufacturing process introduces defects in chips, Automated Test Equipment (ATE) is necessary to discard defective chips. Testing is done by applying stimulus data to the chip inputs and evaluating the measured response data. However, the large amount of test data makes testing expensive. If the amount of test data continues to increase, test costs may even exceed the manufacturing costs for certain products. A promising solution is to transmit compressed stimulus data from the ATE to the chip. Extra circuitry on the chip decompresses the stimulus data and compresses the response data. The three important aspects of the solution are presented: (1) stimulus compression, (2) response compression, and (3) test quality.
Test stimulus data consists of bits that are used to explicitly target faults (care bits) and bits that can be chosen freely (don’t care bits). A new stimulus data compression technique that uses a Linear Feedback Shift Register (LFSR) for decompression on the chip is presented. The disadvantages of previous LFSR compression techniques are (1) their inability to exploit the variance in the number of care bits across the stimulus data set and (2) the large LFSR area overhead. By exploiting the variance in the number of care bits, the new technique achieves an order of magnitude improvement in compression and area overhead. The new technique is applied on actual industrial designs and the results are presented.
Test response data consists of known responses and unknown responses (Xs), which are unknown during logic simulation, for example, due to floating busses. The main challenge in test response compression is handling the Xs. Previous compression techniques are unable to handle many Xs without impacting test quality. By fixing the Xs to known values during response compression, the new technique results in high compression ratios in the presence of many Xs without any test quality impact. The new technique is applied on actual industrial designs and the results are presented.
The number of defective parts that pass the test, i.e., the number of test escapes, determines the test quality. Previous work assumes that compression does not impact the number of test escapes. New experimental results from a .35u technology test chip show that this assumption is incorrect. Based on this result, different test coverage metrics, i.e. metrics used to predict the test quality, are evaluated. New techniques and guidelines to reduce the number of test escapes are presented.

报告人简介:

Biography Prof. Dr. Ir. Erik H. Volkerink:

Dr. Volkerink manages Verigy Labs. In this role, he is responsible for university relations, technical trend scanning, as well as managing Verigy’s patent portfolio. He also manages long-term research in Verigy’s Memory Test Solutions Division. Dr. Volkerink serves as a Consulting Professor in the Electrical Engineering Department of Stanford University and as Assistant Director of Stanford’s Center for Reliable Computing.

Dr. Volkerink research area is Semiconductor Design & Test. He is recipient of the Best Paper Award at the CPA conference as well as a Best Paper Award Nomination of the Design Automation Conference (DAC). He is active in many industry-wide activities. For example, he is the Corporate Track Chair of the International Test Conference (ITC), Cost-of-Test Section Lead of the International Technology Roadmap for Semiconductors (ITRS), and Registration Chair of the Pacific Northwest Test Workshop. He was also Keynote Speaker of the Future of ATE Workshop (FATE) at ITC as well as Session Chair at various conferences.

Dr. Volkerink holds a Ph.D. degree in Semiconductor Design & Test from Stanford University (supervised by Prof. McCluskey), a master’s degree in System Modeling & Control, and a bachelor’s degree in Electrical Engineering from the University of Twente. He also completed the Business Administration certificate program from the School of Business (specialized in International Marketing), the Psychology certificate program from the School of Humanities (specialized in Communications & Conflicts), and the Computer Science certificate program from the School of Computer Science (specialized in Programming Paradigms). He completed management classes at The Boston Consulting Group, Heineken, American Management Systems, Royal Dutch Railway and Royal Dutch Telecom, and received a Rotary Youth Leadership Award.

Previously, he worked with Hewlett-Packard Company, Agilent Technologies, and various smaller companies in the Netherlands. In the early 90s he obtained hands-on hardware/software experience while founding a software development organization and completing many vocational schools in the Netherlands. In his spare time, Dr. Volkerink serves as president of the board of the Dutch School Silicon Valley (DSSV): a Dutch language school he founded in 2000.

 
 

 

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