IEEE Electron Devices Society

Distinguished Lecturer Seminar

 

报告题目: CMOS Devices Architectures for Nanoelectronics

 

报告人: Dr. Simon Deleonibus

                   IEEE Fellow, IEEE Distinguished Lecturer

                   Electronic Nanodevices Laboratory

                   CEA-LETI NANOTEC

                   France

 

时间:   2006320(星期一)上午10:0011:00

 

地点:   复旦大学邯郸校区微电子学楼203

 

CMOS Devices Architectures for Nanoelectronics

 

Simon Deleonibus

Electronic Nanodevices Laboratory

CEA-LETI NANOTEC, France

 

ABSTACT

 

Since 1994, the International Technology Roadmap for Semiconductor (ITRS) has been accelerating the scaling of CMOS devices to lower dimensions despite the difficulties that appear in device optimization at the sub 10nm level. Breakthroughs are required to continue scaling at the same rate. Which are the main showstoppers for CMOS scaling? Short channel effects and tunneling in the gate dielectric are at the origin of the showstoppers. Channel, gate stack and source and drain engineering have to be reconsidered for new devices architecture issues. FD SOI (single or multi gate MOSFETs) and strained dual channels will allow solutions to enhance the Ion/ Ioff trade of future low cost System On Chip(SOC) design. Metal gates show promising perspectives to avoid gate dopant depletion. The issue of electron mobility degradation in the channel of HiK isolated MOSFETs will require innovative solutions to be introduced. Supply voltages lower than 1V will require FDSOI architectures and threshold voltage adjust by tuning the gate material workfunction. Laser or Flash Annealing, Plasma Doping will be required to minimize parasitic effects. It will be very difficult to compete with CMOS logic because of the low series resistance required. Due to the important charge retention capabilities, trapping phenomena in Silicon Nanocrystals are exploited for Flash memory applications. By introducing new materials, like Germanium or graphite/Diamond Carbon, Si based CMOS will scale beyond the ITRS as the future SOC Platform allowing the integration of new disruptive devices. Single Electronics and Power Consumption reduction will be major research subjects in the next decades.
 
 

 

Copyright© 2003-2018 复旦大学微电子学院
联系我们