前沿讲座
Design Issues for Nanoscale CMOS and Network-on-Chip

时    间:12月7日下午2:00-4:00
地    点:张江校区微电子楼389教室
Lecturer: Prof. Hannu Tenhunen, Royal Institute of Technology, Sweden

Abstract:
Nanoscale CMOS technologies are posing new challenges to IC designers. Interconnects are becoming the main design limitation and having a deep influence not only to electrical design of circuits but to also constraining the architectural design choices. Furthermore, to manage the electrical design at system level is very challenging unless a well defined design guidelines are established. In this presentation I will review some of the key challenges in electrical design from traditional circuit perspective in nanoscale CMOS. Furthermore, in order to mitigate the impact of interconects, I will also discuss on some new emerging architectural styles like Network-on-Chip. For NoC related structures I will review what new design challenges and issues we are facing when we encapsulate and abstract away the traditional electrical issues, as discussed in the first part of my talk.

Short Bio:
Prof. Hannu Tenhunen received degrees of Diploma Engineer in Electrical Engineering and Computer Engineering from Helsinki University of Technology, in 1982, and Ph.D. in Electrical Engineering from Cornell University, Ithaca, NY, USA, in 1985 with major in Microelectronics and minor in Applied and Engineering Physics (Microfabrication) (in 2.5 years). From September 1985 he started at Tampere University of Technology, Applied Electronics and later at Signal Processing Laboratory as an associate professor. Since January 1992 he has been with Royal Institute of Technology (KTH), Stockholm, where he is a professor of electronic system design and head of ESDlab In 2004 he received prestigious SSF Senior Individual Grant. In 2004 he was awarded Nokia Visiting Fellow grant.

 
 
 

 

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