研究生前沿讲座

时间: 2004年12月29日上午9:30 – 11:00
地点: 计算中心B325

Title: "Review of Current Mixed-Signal Research"

Abstract: This talk gives an overview of the latest mixed-signal IC research undertaken in Carleton University.

Bio:
Tadeusz A. Kwasniewski received the Ph.D. and M.S. degrees from the Institute of Nuclear Research and Warsaw University of Technology, Poland, in 1980 and 1974, respectively. He worked as a Research and Development Engineer in Warsaw??s Institute of Nuclear Research and VOEST Alpine in Austria. In 1983, he joined Lakehead University and in 1985, Carleton University, Ottawa, ON, Canada. At Carleton he has been a member of the VLSI for communications group. Developed one of the first single-bit delta-sigma A/D converter of 4th order, worked on ISDN integrated circuit with Level One Communications, co-authored the new techniques of frequency synthesis ¨C fractional synthesis, pioneered CMOS GigaHertz CMOS VCO and divider design, worked on CMOS RF circuits (for Motorola US), worked on ADSL receiver front end optimization, in 1999 was invited to organize a CMOS 10Gbps Serdes development group at PMC-Sierra, worked on DLL CMOS frequency synthesis, adaptive eye-opening circuits, CMOS CDRs, link optimization and phase detectors. In 2002 formed an Ottawa CMOS Serdes design group for Altera. Currently consulting for Altera Corporation. Author and co-author of over 20 patents, supervised close to 40 Ph.D. and MSc students and authored numerous journal and conference publications. Currently supervises 6 Ph.D. students and 8 MSc. students.

Past Chair of the IEEE Ottawa Section, current member of Board of Directors of IEEE Ottawa Conference Board. Helped to establish and served on the Board of Directors of Solidum Corporation, now IDT Canada. Communicates in English, German, French, Russian and Polish.


Title: "Industry Trends of Serial Communications"

Abstract: This presentation gives an overview of semiconductor and communication industry, with focus on IO evolution, serial IO standards and applications.

Bio:
Shoujun Wang received the B.S. and M.S. degrees in electronics from Shandong University, China, in 1992 and 1995, respectively, and the Ph.D. degree in microwave from Shanghai University, China, in 1998. He was a postdoctoral fellow with the Department of Electronics, Carleton University in 1999, where he developed design tools for RFIC/MMIC. Late in 1999 he joined Carleton VLSI for communications research group to work on CMOS GHz range designs. From 2000 to 2002, he was a Mixed-Signal IC Design Engineer with PMC-Sierra, where he developed a 10Gbps OC-192 transceiver in 0.13mm CMOS. He significantly contributed to the CDR architecture, PISO, SIPO and Tx designs; led the design and test chip evaluation of different styles of CMOS VCOs and proposed a number of broadband circuit techniques. During that period he was also involved in the design of 0.18mm 1Gbps serial interface for a cross-switch chip. Since 2002, he has been a Member of Technical Staff (a level higher than a Senior Design Engineer) with Altera, where he took a major part in the definition and circuit implementation of a 0.25-10Gbps SERDES transceiver in TSMC 90nm CMOS technology. He also contributed to the development of a 0.13mm 3.125Gbps transceiver, which has been integrated into Altera??s Stratix GX family of FPGA products. He has authored and co-authored 15 publications and 16 patents. Following more than two years of involvement with graduate students as an informal advisor and co-supervisor of M. S. students, in October 2004 he has been officially nominated for an Adjunct Research Professor position in the Department of Electronics, Carleton University. His research interests include analog/mixed-signal ICs, high-speed SERDES transceivers, PLLs, CDRs, equalization techniques and data converters. He is also active in following industry standards development efforts where he often contributes through the company representatives.

 
 

 

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