研究生前沿报告:

CMOS Nanoelectronics devices for the
end of the roadmap and beyond

 

Speaker: Dr. S.Deleonibus, CEA-LETI/ NANOTEC France, IEEE Distinguished Lecturer

 

    The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials(Ge, diamond/graphite Carbon, HiK,…), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The control of low power dissipation and short channel effects together with high performance will be the major challenge. offer a second life to CMOS ?

时间:10月22日下午三点


地点:微电子学楼B213

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