报 告 会

 

题  目:  复杂FPGA设计的验证和纠错

 

主讲者:   P Deroux-DauphinPhD.

法国Temento Systems公司CEO

 

时  间:   20041015(周五)

           下午3:304:30

           40分钟演讲,20分钟演示

          (最先进的FPGA设计验证和纠错方案)

 

地  点:   逸夫科技楼3号会议室

Note: Temento Systems公司有意向复旦学生提供使用其所介绍的最先进的测试和纠错产品

LECTURER

P Deroux-Dauphin, PhD

CEO, Temento Systems


 

VERIFYING AND DEBUGGING COMPLEX FPGAs DESIGNS

  

Friday 15th, October Fudan University

3:30pm~4:00pm:   #3 Meeting Room, Building of Yi-Fu Sci. & Tech.


Abstract

 The density and complexity of FPGAs continue to grow at an incredible rate with multi-millions gates capability, embedded microprocessors, IPs logic blocks and multiple interface standards. As more logic and functionality is incorporated, traditional verification and debug strategies are becoming inadequate and the debugging of FPGA designs is becoming more and more difficult. To save time and money and to get your product to market as quickly as possible, you now must minimize the design verification time. Through this presentation, the LECTURER will provide a new approach of FPGA and SoC physical verification by introducing advanced methodologies and tools that has been developed and optimized specifically for physical design debugging and understanding.


About the author:


Patrice Deroux-Dauphin is President & CEO of Temento Systems SA. He has over 20 years experience in microelectronic and development tools at CEA-LETI and Thales and has bring a large contribution in the development of advanced test and debugging tools and methodologies. M Deroux-Dauphin has a PHD degree in Microelectronics from Institut National Polytechnique de Grenoble - France. He is the author of several patents, and international communication papers. He received the Seymour Cray price in 1990 for his work on the integrated magnetic head.

 
 

 

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