研究生前沿报告

 

题 目:“Statistical Timing Analysis and Design Techniques for Variation Tolerance”

时 间2004年9月10日(星期五),下午3:30。

地 点:计算中心北楼325室。

报告人:Yibin Ye
         Staff scientist in Circuit Research Lab, Intel Labs, Intel Corp.

Abstract:

    Process variations are due to uncertainty in device and interconnect characteristics, such as effective gate length, doping concentration, oxide thickness. Technology scaling has led to the growing impact of process variations on circuit performance. While inter-die variations are modeled by case analysis in static timing analysis, the increasing dominance of within-die process variations create a need for statistical timing analysis. It is important to predict the performance of a chip as a probabilistic quantity.

    In this talk, we will review the progresses made in recent years in statistical timing analysis, and discuss examples of variation-tolerant designs, including dynamic Vcc and adaptive body-bias techniques and their applications in digital and memory circuits.

Speaker’s bio:

    Yibin Ye is a staff scientist in Circuit Research Lab, Intel Labs, Intel Corp. He received his MS degree in Physics from Fudan University in 1988, and taught physics at Ningbo University afterwards. He received MSEE and Ph.D. degrees in Electrical and Computer Engineering from Purdue University in 1994 and 1997, respectively. He has published more than 20 papers in circuit area. He is inventor/co-inventor of 21 issued patents and several pending patents. His current research interests include high performance and low power circuits, memory design, logic synthesis and optimization.

 
 

 

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