讲座信息
Next Paradigm in Silicon and Packaging Technology

 

Lecturer: Prof Rao R. Tummala, Packaging Research Center, Georgia Tech

Time: 10:00 a.m. – 11:00 a.m. June 30, 2004

Place: B325 Computer Center, Fudan University

Abstract:

So called “packaging”, in the past, played two roles: 1) Provide I/O connections to the semiconductor devices so the IC is tested and ready for board assembly. This is called IC packaging; and 2) Integrate components into systems to form end product systems such as cell phones, PDAs, Laptops. This is called systems packaging.?

Both were accomplished by interconnections or wiring at the package or board level.?More recently, the IC devices themselves began to integrate more and more transistors and functions, leading to what the community has been calling SOC or System– on-Chip with multiple systems functions in a single chip. This can be called horizontal or 2D integration of IC blocks toward system-level functionality. The community began to realize, however, that such an approach presents design complexity and fundamental limits for computing, and integration limits for wireless systems, over the long run. This led to 3-D packaging approaches, often referred to as SIP or System-in-Package. Both these are the latest and most leading-edge technologies pushing the IC integration in two and three dimensions, But they both have one major shortcoming.?They depend on CMOS processing and hence are limited by what can achieved with CMOS. The SIP and SOC approaches, while providing major opportunities in both miniaturization and integration for advanced portable and desktop electronic products, are limited by CMOS processes.

A new concept called SOP or System–on–Package – where the package, and not the board, is the entire system – is beginning to address the shortcomings of both SOC and SIP in two ways: Optimize silicon for what it is good for and the package for what it is best at, by means of IC/package/system co-design. While doing so, optimize both for cost, performance, miniaturization and reliability.?The package, in this concept, therefore overcomes both computing limitations and integration limitations of SOC and SIP.?It does this by having global wiring as well as RF and optical component integration in the package level and not in the chip. The SOP, therefore, includes embedded digital, RF and optical components and functions built into a highly miniaturized package, module or board for emerging convergent systems of tomorrow. This Moore’s Law for systems Integration is akin to Moore’s Law for ICs, pushing component density by a factor of 100 to 10,000 by means of microscale thin film component integration in the short term to nanoscale integration in the long term.

 

Bio:

Prof. Rao Tummala is a Distinguished and Endowed Chair Professor at Georgia Tech. He is also the Founding Director of the NSF- Engineering Research Center called PRC, pioneering System-On-Package (SOP) vision for Electronic systems of the next decade. Prior to joining Georgia Tech, he was an IBM Fellow, having pioneered such major technologies as the first flat panel display based on gas discharge, the first and next two generations of multichip packaging based on 35- layer alumina and 61 layer LTCC with copper and materials for ink-jet printing and magnetic storage.

He received many industry, academic and professional society awards including: Industry Week’s award for improving U.S. competitiveness, David Sarnoff award and Major Education award from IEEE, Dan Hughes award from IMAPS, Engineering Materials Achievement award from ASM-International, Total Excellence in manufacturing award from SME, John Jeppson’s award from the American Ceramic Society as well as the Distinguished Alumni Awards from the University of Illinois, the Indian Institute of Science and Georgia Tech.

Prof. Tummala published 345 technical papers, holds 71 patents and inventions, authored the first modern packaging reference book (1988) and the first textbook (2001). He is a fellow of IEEE, IMAPS, the American Ceramic Society, a member of the National Academy of Engineering and was President of the IEEE-CPMT Society and IMAPS Society.

 
 

 

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