最终学位:博士   专业:微电子学与固体电子学     获得年月和院校:1999 复旦大学

现工作单位:复旦大学 系统与专用集成电路国家重点实验室     职称:副教授

联系方法:

Email fengzhou@fudan.edu.cn

通信地址:200433 上海邯郸路 220# 微电子系

 

工作简历(获博士学位后)

2011 - 今      复旦大学 系统与专用集成电路国家重点实验室

专注电子线路教学。“高频电子线路”、“高频电子线路实验”、“模拟数字电路实验”

2006 - 2011   复旦大学 系统与专用集成电路国家重点实验室

研究项目:

1.太阳能光伏系统专用控制芯片(2009年AM基金项目,负责人)

2.集成数字电源芯片 (国家创新基金项目、上海市创新基金项目,负责人)

3.AMOLED驱动芯片 (企业合作项目, 负责人)

2002.7-2005   复旦大学 系统与专用集成电路国家重点实验室

研究项目:

1.防碰撞算法的低功耗实现(国家自然科学基金项目,负责人)

2.射频电子标签(RF-ID)芯片和系统开发(国家863项目,副组长)

3.电源专用集成电路芯片的研究开发

4.低功耗模拟电路、低功耗系统设计方法学研究

2001.11-2002.7 University of California, San Diego, US

美国 加州大学 圣地亚哥分校,博士后。

研究项目:

1.片上系统布线资源优化

2.数模混合电路布局规划

1999.3-2001.10  复旦大学 原电子工程系

负责项目:

1.模拟集成电路原理分析和设计:Modem收发芯片、DC-DC电压转换器、CMOS 8位逐次比较型AD转换器IP、低躁声放大器、功率放大器。

2.数字集成电路设计:序列密码加密解密电路、FPGA单元电路。

 

授权发明专利

  • 200710043462.1 适用于数字电源控制器的混合型数字脉宽调制器
  • 200610029168.0 高线性度CMOS模拟开关
  • 200710037199.5 一种单相功率时钟控制的能量回收电路
  • 200610029169.5 适用于低电压的高线性度CMOS模拟开关
  • 200710037202.3 适用于数字电源控制器的电压/频率型模数转换器
  • 200710043704.7 适用于数字电源控制器的窗口式Flash模数转换器
  • 200910047605.5 一种低压极低功耗电压基准源

教学论文
周锋, “高频电子线路”理论课内嵌实验的探讨,电气电子教学学报,2016年,第三期,第1-3页。

 

PUBLICATIONS

  1. Zhe Zhao, Feng Zhou and Shengzhuang Huang. All-CMOS temperature compensated current reference, Journal of Semiconductors. Vol. 31, No. 6, June 2010
  2. H.F.Ma, Zhou Feng, etc., Full On-chip and Area-efficient CMOS LDO with Zero to Maximum Load Stability Using Adaptive Frequency Compensation, Journal of Semiconductor, vol.31, pp015006, 2010.
  3. Lv Changhui, Zhou Feng, etc. Supply High Voltages with Single-Inductor Multiple-Output DC-DC Buck Converter,Chinese Journal of Electronics, vol.38, pp493-496,2010.
  4. H. F. Ma, F. Zhou, Q. Niu, and C. H. Lv, “Nested Miller Active-Capacitor Frequency Compensation for Low-power Three-stage Amplifiers,” Journal of Semiconductors, vol.29, pp.95, Sept., 2008.
  5. H. F. Ma, and F. Zhou, “Nested Miller Active-Capacitor Frequency Compensation for Low-power Three-stage Amplifiers,” IEEE International Conference on Electron Devices and Solid-State Circuits, Hong Kong, Dec, 2008.
  6. H. F. Ma, and F. Zhou, “A Full On-chip Low-dropout Linear Regulator with Enhanced Line, Load Regulation,” IEEE International Conference on Electron Devices and Solid-State Circuits, Hong Kong, Dec, 2008.
  7. Li Shun, Chen Hua, Zhou Feng, A Novel Technique for Improving Temperature Independency of Ring-ADC, Design, Automation & Test in Europe, March, 2008, Munich, Germany, PP.694-697
  8. Chen Hua, Li Shun, and Zhou Feng,A Novel Hybrid DPWM for Digital DC-DC Converter, Chines Journal of Semiconductor, Feb., 2008, pp65-70 .
  9. Li Shun, Chen Hua, Zhoufeng, A Novel Technique for Improving Temperature Independency of Ring-ADC, Chinese Journal of Semiconductor, Feb., 2008, pp29-33 .
  10. Li Shun, Zhoufeng, etc.,Quasi-Static Energy Recovery Logic with Single Power-Clock Supply, Chinese Journal of Semiconductor, Nov., 2007, pp1729-1734 .
  11. Hua Chen, Shun Li, Qi Niu, Yipin Wu and Feng Zhou, "A Multi-Phase Self-Sensing Clock Generator for Hybrid DPWM Application", The 7th International Conference on ASIC, October, 2007, Guilin, China, pp635-638.
  12. H.Chen, Zhou Feng, S.Li,etc, Design of a Non-bandgap Voltage Reference and Its Characteristic Analysis, Research & Progress of Solid State Electronics(Chinese), Mar., 2008, pp1-5.
  13. Wu Yipin, Zhou Feng,Chen Chunhong,etc., High-level Power Estimation with Improved Entropy for Considering the Temporal Correlated Signals, IEEE International Conference on Communications,Circuits and Systems, Fukuoka, Japan, July,2007
  14. Chunhong Chen, Zhou Feng, Toward Reliability Improvement for Nanoelectronic Circuits Using Gate Replication, IEEE Int. Conf. on Nanotechnology, Aug 2007, Hong Kong, China
  15. Shun Li, Feng Zhou, Hua Chen and Yipin Wu,“Quasi-Static Energy Recovery Logic with Single Power-Clock Supply”,IEEE International Symposium on Circuits and Systems,New Orleans, USA, May, 2007.
  16. Wu YiPing, Zhou Feng, etc., "An Improved Entropy to Estimate Power for Considering Temporal Correlation at High-level", Chinese Journal of Electronics, No.5, 2007
  17. ZHU Wenbin,PENG Yunfeng,YAN Wei,ZHOU Feng,CHEN Hua,“A 10bit 50MHz Resistor String Digital-to-Analog Converter”,Microelectronics (Chinese), No 2 , 2007.
  18. Yunfeng Peng,Wei Yan, Derui Kong and Feng Zhou, "A Novel Technique for Improving the Linearity of the sampling switch" IEEE International Conference on Communications, Circuits and Systems, Guilin, June,2006
  19. Peng Yunfeng, and Zhou Feng “A Novel Sampling switch suitable for Low-Voltage Analog-to-Digital Converters”. Chinese Journal of Semiconductor, vol.27, No.8, August 2006.
  20. Peng Yunfeng, Kong Derui, and Zhou Feng “Design and Implementations of a novel area-efficient Interpolator”. Chinese Journal of Semiconductor, vol.27, No.7, July 2006.
  21. Yunfeng Peng, Derui Kong and Zhou Feng, “A Low-Voltage Sampling switch with Improved Linearity”, IEEE Canadian Conference on Electrical and Computer Engineering, Ottawa, May, 2006
  22. Zhou Feng, Chunhong Chen, etc., “Evaluating and Optimizing Power Consumption of Anti-collision Protocols for Applications in RFID System”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, California, August, 2004
  23. Chunhong Chen, Zhou Feng, etc., "A high-level optimization scheme for low power clock design", 46th IEEE International Midwest Symposium on Circuits and Systems, Cairo, Egypt, Dec 2003.
  24. Feng Zhou, Dawei Jin, Chenling Huang, Min Hao, Optimize the Power Consumption of Passive Electronic Tags for Anti-collision Schemes, 5th International Conference on ASIC, Beijing, Oct., 2003
  25. F. Zhou, E.Y. Cheng, B. Yao, C.K. Cheng, and R. Graham, A Hierarchical Three-Way Interconnect Architecture for Hexagonal Processors, ACM International Workshop on System Level Interconnect Prediction, Monterey, California, April, 2003
  26. H. Chen, F. Zhou, and C.K. Cheng, "The Y-architecture: Yet Another On-chip Interconnect Solution," Asia and South Pacific Design Automation Conference, Kitakyusyu, Japan, Jan., 2003
  27. E.Y. Cheng, F. Zhou, B. Yao, C.K. Cheng, and R. Graham, "Balancing the Interconnect Topology for Arrays of Processors between Cost and Power," IEEE Int. Conf.  on Computer Design, Freiburg, Germany, Sept. 2002.
  28. H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "Physical Planning of On-Chip Interconnect Architectures," IEEE Int. Conf. on Computer Design, Freiburg, Germany, Sept. 2002.
  29. Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng, Refined Single Trunk Tree: A Rectilinear Steiner Tree Generator for Interconnect Prediction, ACM/IEEE International Workshop on System Level Interconnect Prediction, Del Mar, California, USA, 2002
  30. Guo Debing, Zhou Feng, Tang Pushan, “Design of a 900MHz 20mW CMOS Power Amplifier”  Microelectronics (Chinese) No. 1, 2002 
  31. Guo Binlin, Zhou Feng, Tong Jiarong, “A Novel Configurable Analog Unit Architecture” The 4th International Conference on ASIC, Shanghai, China, 2001
  32. Huang Zhijun, Zhou Feng, Tong Jiarong, “A new Programmable Module for Datapath-Specific FPGA” Computer Structure and Design (Chinese), Vol.21, No.3, 2000
  33. Zhou Feng, Huang Zhijun, Tong Jiarong, "An Analytical Delay Model for SRAM-based FPGA Interconnection" Asia and South Pacific Design Automation Conference, Hong Kong, Jan., 1999
  34. Zhou Feng, Tong Jiarong, Tang Pushan, “FPGA routing with special time constraints” Chinese Journal of SemiconductorsVol. 20, No.9 , 1999
  35. Zhou Feng, Tong Jiarong, Tang Pushan, “A new algorithm for FPGA placement”Computer Aid Design & Computer Graphics (Chinese), Vol. 11, No.4 , 1999

BOOk

Zhou Feng, Bo Yao, Chung-Kuan Cheng, “Chapter 53, Floorplan Representation in VLSI” of “Data Structures and Applications”, CHAPMAN&HALL/CRC (US)

 

TECHNICAL REPORTS

Feng Zhou, Dawei Jin, Chenling Huang, Hao Min, Optimize the Power Consumption of Passive Electronic Tags for Anti-collision Schemes, XI AutoID Center Board Meeting, Tokyo, Oct, 2003

 

TUTORIALS

F. Zhou, Chung-Kuan Cheng, VLSI CAD: Floorplanning. University of California, San Diego

 

 

 
 
 

 

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