殷韵,女,博士,讲师。主要从事模拟射频集成电路方向的研究。2010年获清华大学微机电系统工程专业学士学位,2015年获清华大学电子科学与技术专业博士学位。2015年7月加入复旦大学微电子学院从事科研与教学工作。作为主要技术骨干,参与完成两项“新一代宽带无线移动通信网”国家科技重大专项以及两项与华为企业级合作项目,主导研发多款多模多带无线收发机芯片。作为第一作者在国际重要固态电路期刊(T-MTT、TCAS-I等)和固态电路会议(CICC、ASSCC等)上发表文章10余篇。

研究兴趣:

  1. 模拟射频集成电路与系统设计:
    a) 多模多带射频前端芯片设计技术;
    b)低功耗物联网收发机芯片设计技术;
  2. 高效率CMOS功率放大器设计技术研究;

联系方式:
通信地址:上海市张衡路825号微电子楼217室 201210
电子邮箱:yiny@fudan.edu.cn

代表性论文:

    1. Y. Yin, X. Yu, Z. Wang et al. An efficiency-enhanced stacked 2.4-GHz CMOS power amplifier with mode switching scheme for WLAN applications. IEEE Transactions on Microwave Theory and Techniques, 2015, 63(2): 672-682. (第一作者)
    2. Y. Yin, B. Chi, Y. Gao et al. A 0.1-5.0GHz reconfigurable transmitter with dual-mode power amplifier and digitally-assisted self-calibration for private network communications. IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61(11): 3266-3277. (第一作者)
    3. Y. Yin, B. Chi, Z. Xia et al. A reconfigurable dual-mode CMOS power amplifier with integrated T/R switch for 0.1-1.5GHz multi- standard applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(7): 471-475. (第一作者)
    4. Y. Yin, B. Chi, Z. Sun et al. A 0.1-6.0GHz dual-path SDR transmitter supporting intraband carrier aggregation in 65nm CMOS. IEEE Transactions on Very Large Scale Integration Systems. (第一作者)
    5. Y. Yin, B. Chi, Z. Wang. Efficiency-enhanced self-biased PA driver for multi-standard applications. Electronics Letters, 2014, 50(13), 927-928. (第一作者)
    6. Y. Yin, Y. Gao, Z. Wang, B. Chi. A 0.1-5.0GHz self-calibrated SDR transmitter with -62.6dBc CIM3 in 65nm CMOS. IEEE Custom Integrated Circuits Conference, CICC, 2015: 1-4. (第一作者)
    7. Y. Yin, B. Chi, X. Yu et al. An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications. IEEE Custom Integrated Circuits Conference, CICC, 2014: 1-4. (第一作者)
    8. Y. Yin, B. Chi, Q. Yu et al. A 0.1-5GHz SDR transmitter with dual-mode power amplifier and digitally-assisted I/Q imbalance calibration in 65nm CMOS. IEEE Asian Solid-State Circuits Conference, A-SSCC, 2013, 205-208. (第一作者)
    9. Y. Yin, B. Chi, Z. Wang. A 0.1-1.5GHz dual-mode Class-AB/ Class-F power amplifier in 65nm CMOS. IEEE International Midwest Symposium on Circuits and Systems, MWSCAS, 2013. (第一作者)
    10. X. Zhang, Y. Yin, M. Cao et al. A 0.1-4GHz receiver and 0.1- 6GHz transmitter with reconfigurable 10-100MHz signal bandwidth in 65nm CMOS. IEEE Custom Integrated Circuits Conference, CICC, 2012: 1-4.
    11. Y. Gao, Y. Yin, W. Jia et al. A reconfigurable digital intermediate frequency module for software defined radio transmitters. IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT, 2014, 1-3.
    12. X. Yu, M. Wei, Y. Yin et al. A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS. IEEE Journal of Solid-State Circuits, JSSC, 2015.
    13. X. Yu, M. Wei, Y. Yin et al. A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS. IEEE Asian Solid-State Circuits Conference, A-SSCC, 2014, 257-260.
    14. X. Yu, M. Wei, Y. Yin et al. A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, 2015.
    15. Z. Song, X. Liu, X. Zhao, Q. Liu, Z. Jin, Y. Yin, Y. Sun, B. Chi. A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, 2015.
 
 
 
 

 

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