薛晓勇

职称:副研究员+硕士生导师
办公地址:张江校区微电子楼205室
电话:021- 51355200-987
E-mail:xuexiaoyong@fudan.edu.cn

 

研究兴趣:
面向神经形态计算、存储计算、机器学习和高性能存储系统的数模混合集成电路设计

研究内容:
1. 面向区块链和电子货币的高性能存储系统设计:区块链和电子货币的发展带来计算和存储资源的巨大消耗,该项目针对现有分布式计算和存储的应用诉求,研究高性能的存储、计算系统和软件架构。
2. 新型神经形态器件及芯片集成基础研究:深度学习在人工智能中的应用方兴未艾,神经形态计算作为替代技术引起重点关注,本项目结合神经科学原理和集成电路技术,开发面向类脑人工智能的器件、电路、架构和算法等关键技术。
3. 基于忆阻器面向IoT终端SOC的可重构存储计算研究:IoT终端数量日益增长,信息安全和低功耗是其主要诉求。本项目研究基于新型器件、存算合一的新型计算架构,并针对各种加密算法进行协同设计,从而克服传统冯洛伊曼架构存算分离在功耗、集成度和信息安全方面的缺陷。
4. 忆阻器在嵌入式深度学习中的应用研究:现有机器学习的硬件平台CPU、GPU、FPGA、TPU和ASIC(SOC)在性能和能效方面仍需提升,才能满足IoT终端、手持设备、可穿戴设备等智能终端在线学习、实时响应、超长待机等需求,本项目研究基于新型器件的机器学习(深度学习)加速技术来满足上述需求。
5. 忆阻器在高密度非易失TCAM中的应用研究:TCAM在高端路由和大数据搜索中有非常重要的应用,但其容量的提升导致面积和功耗增加过快。本项目结合新型器件的高密度特性和机器学习的智能化优势,实现TCAM的高密度和低功耗。

发表情况:
专著及章节:

[1] Yinyin Lin, Yali Song, Xiaoyong Xue,Resistive memory: device, material, mechanism, reliability and circuits,Science Press China, 2014 (ISBN:9787030414991)
[2] Yinyin Lin, Yali Song, Xiaoyong Xue, RRAM device and circuit in Data Storage at the Nanoscale: Advances and Applications (Edited by Fuxi Gan and Yang Wang), Pan Stanford Publishing Pte. Ltd. (2015). (ISBN: 978-981-4613-19-4 (Hardcover), 978-981-4613-20-0 (eBook)

期刊论文:
[4] Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, and Jingang Wu, Dynamic Data-dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), vol. 64, no. 2, pp. 186-190, 2017.
[5] Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, QinTian Zou, JinGang Wu, A self-adaptive write driver with fast termination of step-up pulse for ReRAM, IEICE Electronics Express (ELEX), vol. 13, no. 7, p. 20160195, 2016.
[6] Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu, A logic resistive memory chip for embedded key storage with physical security, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), vol. 63, no. 4, pp. 336-340, 2016.
[7] X. Xue, J. Yang, Y. Lin, R. Huang, Q. Zou and J. Wu, Low-Power Variation-Tolerant Nonvolatile Lookup Table Design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 24, no. 3, pp. 1174-1178, 2016.
[8] Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, and Jingang Wu, A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction, IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 5, 2013.

会议论文:
[9] Keji Zhou, Xiaoyong Xue, Jianguo Yang, etc, Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction, IEEE Asian Solid-State Circuits Conference (ASSCC), 2018.
[10] Jianguo Yang, Xing Li, Tao Wang, Xiaoyong Xue, etc. A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM, IEEE European Solid-State Circuits Conference (ESSCIRC), 2018.
[11] Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin, ReRAM Write Circuit with Dynamic Uniform and Small Overshoot Compliance Current under PVT Variations, IEEE International Conference on ASIC (ASICON), pp. 16-19, 2017.
[12] Yun Yin, Tong Li, Xiaoyong Xue, A 1.0-3.0GHz LTE Transmitter with CIM Enhancement, IEEE International Conference on ASIC (ASICON), pp. 1135-1138, 2017.
[13] Yang, J., Y. Lin, Y. Fu, X. Xue, and B.A. Chen. A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application, IEEE International Symposium on Circuits and Systems (ISCAS), 2017.
[14] Yarong, F., X. Juan, Z. Yanqing, X. Xiaoyong, and L. Yinyin. A SPICE model of bi-layer resistive random access memory with stepped reset phenomenon, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016.
[15] Yinyin Lin, Xinyi Hu, Jianguo Yang, and Xiaoyong Xue, A Compact Pico-second In-situ Sensor Using Programmable Ring Oscillators for Advanced On Chip Variation Characterization in 28nm HKMG, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 13-16 , 2016.
[16] Zhao, Y., J. Xu, J. Yang, X. Xue, Y. Lin, and J. Sim, Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression, IEEE International Symposium on Circuits and Systems (ISCAS), 2016.
[17] Yinyin Lin, Y. Rui, Xiaoyong Xue, and B. A. Chen, 3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance, in Circuits and Systems (ISCAS), IEEE International Symposium on Circuits and Systems (ISCAS), pp. 377-380, 2015.
[18] Yang, R., X. Xue, Y. Xie, and Y. Lin, Adaptive block level management for hybrid main memory, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014.
[19] Meng, Y., X.Y. Xue, Y.L. Song, J.G. Yang, B.A. Chen, Y.Y. Lin, Q.T. Zou, R. Huang, and J.G. Wu, Fast step-down set algorithm of resistive switching memory with low programming energy and significant reliability improvement, IEEE Symposium on VLSI Technology (VLSIT), 2014.
[20] Yang, J., M. Ying, X. Xue, R. Huang, Q.T. Zhou, J.G. Wu, and Y. Lin, A 2Mb ReRAM with two bits error correction codes circuit for high reliability application, IEEE International Conference on ASIC (ASICON). 2013.
[21] Song, Y.L., Y. Meng, X.Y. Xue, F.J. Xiao, Y. Liu, B. Chen, Y.Y. Lin, Q.T. Zou, R. Huang, and J.G. Wu, Reliability significant improvement of resistive switching memory by dynamic self-adaptive write method, IEEE Symposium on VLSI Technology (VLSIT), 2013.
[22] X.Y. Xue, C. Meng, C.L. Dong, B. Chen, Y.Y. Lin, R. Huang, Q.T. Zou, J.G. Wu, A Logic-Based Embedded DRAM with Novel Cell Structure and Dynamically Adaptive Refresh for Long Data Retention, Zero Data Availability Penalty and High Yield, International Memory Workshop (IMW), pp. 132-134, 2013.
[23] Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, and Jingang Wu, A 0.13μm 8Mb Logic Based CuxSiyO Resistive Memory with Self-Adaptive Yield Enhancement and Operation Power Reduction, IEEE Symposium on VLSI Circuits (VLSIC), pp. 42-43, 2012.
[24] Chen G, Xue X, Dong Q, et al. A novel low power wide supply voltage range CMOS temperature sensor with -0.2/0.5° C error from -20° C to 60° C, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, 2012.
[25] Dong, Q., Y. Ma, H. Chen, H. Li, Y. Jiang, N. Liu, W. Jian, X. Xue, L. Chen, J. Wang, J. Kim, S. Yu, J. Wu, and Y. Lin. A novel method for accurate measurement and decoupling of SRAM standby leakage, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2012.
[26] Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin, Novel RRAM programming technology for instant-on and high-security FPGAs, IEEE International Conference on ASIC (ASICON), pp. 291-294, 2011.

 
 
 
 

 

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